In general, a gate-coupling coefficient may be an important element to determine an efficiency of a memory cell in a 0.13 μm or less-grade flash memory device. The gate-coupling coefficient may have a substantial effect on an electric potential of a floating gate. In a flash memory device having a higher gate-coupling coefficient, the electric potential of the floating gate may be adjacent to a given electric potential of a control gate in the memory cell. Accordingly, performance of a flash memory cell may be improved, including programming and erasing efficiency and rapid reading speed.
The high gate-coupling rate may enable a simplification of chip design, and may lower an operation voltage of a flash memory cell to a lower power-source voltage. That is, an important element to determine the gate-coupling coefficient may be a capacitance between each polysilicon to a tunnel oxide capacitance, that is, a capacitance between a floating gate poly and a control gate poly. As the capacitance between each polysilicon increases and the tunnel oxide capacitance decreases, the gate coupling-coefficient may increase.
FIG. 1 illustrates a stack gate structure of a flash memory device according to the related art. By increasing a surface area of a capacitor between polysilicons 13 and 15 or decreasing a thickness of ONO layer 14, a capacitor effect between polysilicons 13 and 15 may increase. However, as the thickness of ONO layer 14 decrease, an efficiency of a floating gate to store charge carriers may be lowered. In this respect, it may be difficult to decrease the thickness of ONO layer 14 by a large extent.
In fabrication technology for a nonvolatile memory, such as a flash memory device, the thickness of ONO layer 14 may be decreased to a minimum value or its approximation above a predetermined thickness which may be suitable for charge-storing capacity within the floating gate. Also, the gate-coupling coefficient may become higher as the ratio of the surface area of capacitor between polysilicons 13 and 15 to the surface area of tunnel oxide 12 increases. In this case, the surface area of the ONO capacitor may be determined based on a height of the polysilicon and a total width of the polysilicon including an overlap region between floating gate 13 and STI region 11 of substrate 10. Also, the surface area of tunnel oxide capacitor 12 may be determined based on a width of an active cell. Accordingly, the gate coupling may be improved by increasing an overlap region between floating gate 13 and the insulation layer.
To determine the interval between each floating gate, it may be necessary to increase a size of the insulation layer. However, increasing size of the insulation layer may cause an increase in cell size. Accordingly, due to the general trend to decrease cell size, which may cause the decrease in width of active cell of flash memory transistor, the decrease of interval between the insulation layers, and the decrease in the overlap region between the STI and the floating gate, a cell structure and a method of forming a cell structure to improve the gate-coupling coefficient of the nonvolatile memory transistor have been proposed to decrease the size of transistor without the decrease in efficiency of memory chip.